MS THESIS PRESENTATION: High Level Synthesis Based FPGA Implementation of Matricized Tensor Times Khatri-Rao Product to Accelerate Canonical Polyadic Decomposition
Zahit Saygın Doğu
(Supervisor: Prof. Dr. Cevdet Aykanat )
(Co-supervisor: Assoc. Prof. Dr. M. Mustafa Özdal)
Computer Engineering Department
Tensor factorization has many applications such as network anomaly detection, structural damage detection and music genre classification. Most time consuming part of the CP-ALS based tensor factorization is the Matricized Tensor Times Khatri-Rao Product (MTTKRP). In this thesis the goal was to show that an FPGA implementation of the MTTKRP kernel can be comparable with the state of the art software implementations. To achieve this goal, a flat design consisting of a single loop is developed using Vivado HLS. In order to process the large tensors with the limited BRAM capacity of the FPGA board, a tiling methodology with optimized processing order is introduced. It has been shown that tiling has a negative impact on the general performance because of increasing DRAM access per subtensor, however with the minimum tiling possible to process the tensors; the FPGA implementation achieves up to 3.40 speedup against the single threaded software.
DATE: 08 August 2019, Thursday @ 15:45